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Quad, 12-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter AD9228
FEATURES
4 ADCs integrated into 1 package 119 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 82 dBc (to Nyquist) Excellent linearity DNL = 0.3 LSB (typical) INL = 0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 315 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode
FUNCTIONAL BLOCK DIAGRAM
AVDD PDWN DRVDD DRGND
AD9228
VIN + A VIN - A VIN + B VIN - B VIN + C VIN - C VIN + D VIN - D VREF SENSE REFT REFB REF SELECT PIPELINE ADC
12 SERIAL LVDS 12 PIPELINE ADC 12 PIPELINE ADC 12 PIPELINE ADC SERIAL LVDS SERIAL LVDS D+C D-C D+D D-D SERIAL LVDS D+B D-B D+A D-A
+ -
FCO+ 0.5V SERIAL PORT INTERFACE DATA RATE MULTIPLIER FCO- DCO+ DCO-
Figure 1.
APPLICATIONS
Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment
capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individualchannel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI). The AD9228 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of -40C to +85C.
GENERAL DESCRIPTION
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
PRODUCT HIGHLIGHTS
1. 2. 3. Small Footprint. Four ADCs are contained in a small, spacesaving package. Low power of 119 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9259 (14-bit).
4. 5.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006-2007 Analog Devices, Inc. All rights reserved.
05727-001
RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK-
AD9228 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 AC Specifications.......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagrams.............................................................................. 7 Absolute Maximum Ratings............................................................ 9 Thermal Impedance ..................................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Equivalent Circuits ......................................................................... 12 Typical Performance Characteristics ........................................... 14 Theory of Operation ...................................................................... 19 Analog Input Considerations ................................................... 19 Clock Input Considerations...................................................... 22 Serial Port Interface (SPI).............................................................. 30 Hardware Interface..................................................................... 30 Memory Map .................................................................................. 32 Reading the Memory Map Table.............................................. 32 Reserved Locations .................................................................... 32 Default Values ............................................................................. 32 Logic Levels................................................................................. 32 Evaluation Board ............................................................................ 36 Power Supplies............................................................................ 36 Input Signals................................................................................ 36 Output Signals ............................................................................ 36 Default Operation and Jumper Selection Settings................. 37 Alternative Analog Input Drive Configuration...................... 38 Outline Dimensions ....................................................................... 52 Ordering Guide .......................................................................... 52
REVISION HISTORY
7/07--Rev. A to Rev. B Changes to Figure 3.......................................................................... 7 Change to Table 7 ........................................................................... 10 5/07--Rev. 0 to Rev. A Changes to Features.......................................................................... 1 Change to Effective Number of Bits (ENOB) ............................... 4 Changes to Logic Output (SDIO/ODM) Section......................... 5 Added Endnote 3 to Table 3 ............................................................ 5 Changes to Pipeline Latency ........................................................... 6 Added Endnote 2 to Table 4 ............................................................ 6 Changes to Figure 2 to Figure 4 ...................................................... 7 Changes to Figure 10...................................................................... 12 Changes to Figure 15, Figure 17 to Figure 19, Figure 37, and Figure 39 ..................................................................................... 14 Changes to Figure 23 to Figure 26 Captions ............................... 15 Change to Figure 35 Caption ........................................................ 17 Added Figure 46 and Figure 47..................................................... 20 Changes to Figure 51...................................................................... 21 Changes to Clock Duty Cycle Considerations Section.............. 22 Changes to Power Dissipation and Power-Down Mode Section ...23 Changes to Figure 61 to Figure 63 Captions ............................... 25 Changes to Table 9 Endnote.......................................................... 26 Changes to Digital Outputs and Timing Section ....................... 27 Added Table 10 ............................................................................... 27 Changes to RBIAS Pin Section ..................................................... 28 Deleted Figure 62 and Figure 63 .................................................. 27 Changes to Figure 67...................................................................... 29 Changes to Hardware Interface Section ...................................... 30 Added Figure 68 ............................................................................. 31 Changes to Table 15 ....................................................................... 31 Changes to Reading the Memory Map Table Section ............... 32 Change to Input Signals Section................................................... 36 Changes to Output Signals Section.............................................. 36 Changes to Figure 71...................................................................... 36 Changes to Default Operation and Jumper Selection Settings Section........................................... 37 Changes to Alternative Analog Input Drive Configuration Section.................................................... 38 Changes to Figure 74...................................................................... 40 Changes to Table 17 ....................................................................... 48 Changes to Ordering Guide .......................................................... 52 4/06--Revision 0: Initial Version
Rev. B | Page 2 of 52
AD9228 SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 1.
Parameter 1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation at 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation 2 CROSSTALK CROSSTALK (Overrange Condition) 3
1 2
Temperature
Min 12
AD9228-40 Typ Max
Min 12
AD9228-65 Typ Max
Unit Bits
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 1.7 1.7
Guaranteed 1 2 0.4 0.3 0.25 0.4 2 17 21 2 3 6 2 AVDD/2 7 315 1.8 1.8 155 31 335 2 72 -100 -100
8 8 1.2 0.7 0.5 1
Guaranteed 1 2 2 0.3 0.3 0.4 2 17 21
8 8 3.5 0.7 0.65 1
mV mV % FS % FS LSB LSB ppm/C ppm/C ppm/C
30
2 3 6 2 AVDD/2 7 315
30
mV mV k V p-p V pF MHz
1.9 1.9 170 34 367 5.8
1.7 1.7
1.8 1.8 232 34 478 2 72 -100 -100
1.9 1.9 245 38 510 5.8
V V mA mA mW mW mW dB dB
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range.
Rev. B | Page 3 of 52
AD9228
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 2.
Parameter 1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST HARMONIC (Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)-- AIN1 AND AIN2 = -7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz
1
Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Min
AD9228-40 Typ Max 70.5 70.2 70.2 70.0 70.3 69.8 69.7 69.5 11.42 11.37 11.37 11.33 85 82 80 80 -85 -82 -80 -80 -90 -90 -90 -90
Min
AD9228-65 Typ Max 70.2 70.0 70.0 69.5 70.0 70.0 69.8 69.0 11.37 11.33 11.33 11.25 85 85 84 74 -85 -85 -84 -74 -90 -90 -90 -88
Unit dB dB dB dB dB dB dB dB Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc
68.5
68.5
68.0
68.0
11.1
11.1
72
73
-72
-73
-80
-79
25C 25C
80.8 75.0
77.8 77.0
dBc dBc
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Rev. B | Page 4 of 52
AD9228
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 3.
Parameter 1 CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage 2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) 3 Logic 1 Voltage (IOH = 800 A) Logic 0 Voltage (IOL = 50 A) DIGITAL OUTPUTS (D + x, D - x), (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D + x, D - x), (Low Power, Reduced Signal Option) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default)
1 2
Temperature
Min
AD9228-40 Typ Max CMOS/LVDS/LVPECL
Min
AD9228-65 Typ Max CMOS/LVDS/LVPECL
Unit
Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full 25C 25C Full Full
250 1.2 20 1.5 1.2 0 30 0.5 1.2 0 70 0.5 1.2 0 30 2 1.79 0.05 LVDS DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3
250 1.2 20 1.5 1.2 30 0.5 1.2 70 0.5 1.2 0 30 2 1.79 0.05 LVDS 247 1.125 454 1.375 Offset binary DRVDD + 0.3 0.3 3.6 0.3 3.6 0.3
mV p-p V k pF V V k pF V V k pF V V k pF V V
Full Full
247 1.125
454 1.375 Offset binary
mV V
LVDS Full Full 150 1.10 250 1.30 Offset binary 150 1.10
LVDS 250 1.30 Offset binary mV V
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection.
Rev. B | Page 5 of 52
AD9228
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = -0.5 dBFS, unless otherwise noted. Table 4.
AD9228-40 Parameter 1, 2 CLOCK 3 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD) 4 DCO to Data Delay (tDATA)4 DCO to FCO Delay (tFRAME) Data to Data Skew (tDATA-MAX - tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time
4
AD9228-65 Max Min 65 10 10 7.7 7.7 3.5 2.0 2.7 300 300 2.7 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) 50 600 375 8 3.5 Typ Max Unit MSPS MSPS ns ns ns ps ps ns ns ps ps ps ns s CLK cycles ps ps rms CLK cycles
Temp Full Full Full Full Full Full Full Full Full Full Full Full 25C 25C Full
Min 40
Typ
12.5 12.5 2.0 2.7 300 300 2.7 tFCO + (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) 50 600 375 8
2.0
3.5
2.0
3.5
(tSAMPLE/24) - 300 (tSAMPLE/24) - 300
(tSAMPLE/24) + 300 (tSAMPLE/24) + 300 150
(tSAMPLE/24) - 300 (tSAMPLE/24) - 300
(tSAMPLE/24) + 300 (tSAMPLE/24) + 300 150
25C 25C 25C
500 <1 1
500 <1 2
1 2
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured on standard FR-4 material. 3 Can be adjusted via the SPI. 4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
Rev. B | Page 6 of 52
AD9228 TIMING DIAGRAMS
N-1 VIN x
tA
N
CLK-
tEH
tEL
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tPD
D-x MSB N-9 D10 N-9 D9 N-9 D8 N-9 D7 N-9
tDATA
05727-039
D6 N-9
D5 N-9
D4 N-9
D3 N-9
D2 N-9
D1 N-9
D0 N-9
MSB N-8
D10 N-8
D+x
Figure 2. 12-Bit Data Serial Stream, MSB First (Default)
N-1
VIN x
tA
N
tEH
CLK-
tEL
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tPD
D-x MSB N-9 D+x D8 N-9 D7 N-9 D6 N-9 D5 N-9
tDATA
D4 N-9 D3 N-9 D2 N-9 D1 N-9 D0 N-9 MSB N-8 D8 N-8 D7 N-8 D6 N-8 D5 N-8
Figure 3. 10-Bit Data Serial Stream, MSB First
Rev. B | Page 7 of 52
05727-040
AD9228
N-1
VIN x
tA
N
CLK-
tEH
tEL
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tPD
D-x LSB N-9 D+x D0 N-9 D1 N-9 D2 N-9 D3 N-9
tDATA
05727-041
D4 N-9
D5 N-9
D6 N-9
D7 N-9
D8 N-9
D9 N-9
D10 N-9
LSB N-8
D0 N-8
Figure 4. 12-Bit Data Serial Stream, LSB First
Rev. B | Page 8 of 52
AD9228 ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D + x, D - x, DCO+, DCO-, FCO+, FCO-) CLK+, CLK- VIN + x, VIN - x SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To AGND DRGND DRGND DRVDD DRGND Rating -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +0.3 V -2.0 V to +2.0 V -0.3 V to +2.0 V
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL IMPEDANCE
AGND AGND AGND AGND AGND AGND -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -0.3 V to +3.9 V -0.3 V to +2.0 V -0.3 V to +2.0 V -40C to +85C 150C 300C -65C to +150C
Table 6.
Air Flow Velocity (m/sec) 0.0 1.0 2.5
1
JA1 24 21 19
JB 12.6
JC 1.2
Unit C/W C/W C/W
JA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB.
ESD CAUTION
Rev. B | Page 9 of 52
AD9228 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VIN - C VIN + C VIN + B
38 48 47 46 45 44 43 42 41 40 39 37
AVDD 1 AVDD 2 VIN - D 3 VIN + D 4 AVDD 5 AVDD
6
PIN 1 INDICATOR
VIN - B
SENSE
RBIAS
AVDD
AVDD
AVDD
REFB
VREF
REFT
36 35 34
AVDD AVDD VIN - A VIN + A AVDD PDWN CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD
EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE)
33 32
AD9228
31 30 29 28 27 26 25
CLK- 7 CLK+ 8 AVDD
9
TOP VIEW
AVDD 10 DRGND 11 DRVDD
12
13
D + D 14
15
D + C 16
17
D + A 20
21
FCO+ 22
D + B 18
D - A 19
23
24
FCO-
DCO-
Figure 5. 48-Lead LFCSP Pin Configuration, Top View
Table 7. Pin Function Descriptions
Pin No. 0 1, 2, 5, 6, 9, 10, 27, 32, 35, 36, 39, 45, 46 11, 26 12, 25 3 4 7 8 13 14 15 16 17 18 19 20 21 22 23 24 28 29 30 31 33 34 Mnemonic AGND AVDD DRGND DRVDD VIN - D VIN + D CLK- CLK+ D-D D+D D-C D+C D-B D+B D-A D+A FCO- FCO+ DCO- DCO+ SCLK/DTP SDIO/ODM CSB PDWN VIN + A VIN - A Description Analog Ground (Exposed Paddle) 1.8 V Analog Supply Digital Output Driver Ground 1.8 V Digital Output Driver Supply ADC D Analog Input Complement ADC D Analog Input True Input Clock Complement Input Clock True ADC D Digital Output Complement ADC D Digital Output True ADC C Digital Output Complement ADC C Digital Output True ADC B Digital Output Complement ADC B Digital Output True ADC A Digital Output Complement ADC A Digital Output True Frame Clock Output Complement Frame Clock Output True Data Clock Output Complement Data Clock Output True Serial Clock/Digital Test Pattern Serial Data IO/Output Driver Mode Chip Select Bar Power-Down ADC A Analog Input True ADC A Analog Input Complement
Rev. B | Page 10 of 52
DCO+
05727-003
D-D
D-C
D-B
AD9228
Pin No. 37 38 40 41 42 43 44 47 48 Mnemonic VIN - B VIN + B RBIAS SENSE VREF REFB REFT VIN + C VIN - C Description ADC B Analog Input Complement ADC B Analog Input True External resistor sets the internal ADC core bias current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) ADC C Analog Input True ADC C Analog Input Complement
Rev. B | Page 11 of 52
AD9228 EQUIVALENT CIRCUITS
DRVDD
V
VIN x
V D+ V
D- V
05727-030
DRGND
Figure 6. Equivalent Analog Input Circuit
Figure 9. Equivalent Digital Output Circuit
10 CLK+
10k 1.25V 10k 10 CLK-
SCLK/DTP AND PDWN
1k 30k
05727-032
05727-005
Figure 7. Equivalent Clock Input Circuit
Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit
RBIAS
100
SDIO/ODM
350
05727-035
Figure 8. Equivalent SDIO/ODM Input Circuit
Figure 11. Equivalent RBIAS Circuit
Rev. B | Page 12 of 52
05727-031
30k
05727-033
AD9228
AVDD 70k CSB 1k
05727-034
6k
Figure 12. Equivalent CSB Input Circuit
Figure 14. Equivalent VREF Circuit
SENSE
1k
Figure 13. Equivalent SENSE Circuit
05727-036
Rev. B | Page 13 of 52
05727-037
VREF
AD9228 TYPICAL PERFORMANCE CHARACTERISTICS
0 -20 AIN = -0.5dBFS SNR = 70.51dB ENOB = 11.42 BITS SFDR = 86.00dBc
0
-20
AIN = -0.5dBFS SNR = 69.62dB ENOB = 11.27 BITS SFDR = 72.48dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-40
-40
-60
-60
-80
-80
-100
05727-052
-100
05727-054
-120
0
2
4
6
8
10
12
14
16
18
20
-120
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 15. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 40 MSPS
Figure 18. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS
0 AIN = -0.5dBFS SNR = 70.38dB ENOB = 11.40 BITS SFDR = 81.13dBc
0
-20
-20
AIN = -0.5dBFS SNR = 68.74dB ENOB = 11.12 BITS SFDR = 72.99dBc
AMPLITUDE (dBFS)
-40
AMPLITUDE (dBFS)
-40
-60
-60
-80
-80
-100
05727-085
-100
05727-055
-120
0
2
4
6
8
10
12
14
16
18
20
-120
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 40 MSPS
Figure 19. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS
0
-20
AIN = -0.5dBFS SNR = 70.53dB ENOB = 11.42 BITS SFDR = 86.04dBc
0
-20
AIN = -0.5dBFS SNR = 67.68dB ENOB = 10.95 BITS SFDR = 62.23dBc
AMPLITUDE (dBFS)
-40
AMPLITUDE (dBFS)
-40
-60
-60
-80
-80
-100
05727-053
-100
05727-056
-120
0
5
10
15
20
25
30
-120
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 65 MSPS
Figure 20. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 65 MSPS
Rev. B | Page 14 of 52
AD9228
0 AIN = -0.5dBFS SNR = 67.58dB ENOB = 10.93 BITS SFDR = 68.39dBc
84 82 80
AMPLITUDE (dBFS)
-20
2V p-p, SFDR
SNR/SFDR (dB)
-40
78 76 74 72
-60
-80
-100
05727-057
2V p-p, SNR 15 20 25 ENCODE (MSPS) 30 35
-120
0
5
10
15
20
25
30
68 10
40
FREQUENCY (MHz)
Figure 21. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 65 MSPS
Figure 24. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 40 MSPS
0
-20
AIN = -0.5dBFS SNR = 65.56dB ENOB = 10.6 BITS SFDR = 62.72dBc
90
85 2V p-p, SFDR
AMPLITUDE (dBFS)
-60
SNR/SFDR (dB)
-40
80
75
-80
70
-100
05727-058
65 2V p-p, SNR 60 10 20 30 40 50 60
05727-062
-120
0
5
10
15
20
25
30
FREQUENCY (MHz)
ENCODE (MSPS)
Figure 22. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 65 MSPS
Figure 25. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
90
84 82
2V p-p, SFDR
2V p-p, SFDR
85
80
SNR/SFDR (dB) SNR/SFDR (dB)
80
78 76 74 72
75
70 2V p-p, SNR 65
05727-059
2V p-p, SNR 20 30 40 50 60
60 10
15
20
25 ENCODE (MSPS)
30
35
40
68 10
ENCODE (MSPS)
Figure 23. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 40 MSPS
Figure 26. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 65 MSPS
Rev. B | Page 15 of 52
05727-064
70
05727-061
70
AD9228
100 90 80 70 2V p-p, SFDR
100
fIN = 10.3MHz fSAMPLE = 40MSPS
90 80 70
fIN = 35MHz fSAMPLE = 65MSPS
2V p-p, SFDR
SNR/SFDR (dB)
SNR/SFDR (dB)
60 50 40 30 20
05727-065
60 50 40 30 20 10 0 -60 -50 -40 -30 -20 -10 0
05727-070
80dB REFERENCE
2V p-p, SNR 80dB REFERENCE
2V p-p, SNR
10 0 -60 -50 -40 -30 -20 -10 0
ANALOG INPUT LEVEL (dBFS)
ANALOG INPUT LEVEL (dBFS)
Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 40 MSPS
Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 65 MSPS
100 90 80
0
fIN = 35MHz fSAMPLE = 40MSPS
2V p-p, SFDR
-20
AIN1 AND AIN2 = -7dBFS SFDR = 80.75dBc IMD2 = 85.53dBc IMD3 = 80.83dBc
AMPLITUDE (dBFS)
70
SNR/SFDR (dB)
-40
60 50 40 30 20 10 0 -60 -50 -40 -30 -20 -10 0
05727-066
80dB REFERENCE
-60
2V p-p, SNR
-80
-100
05727-049
-120
0
2
4
6
8
10
12
14
16
18
20
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure 28. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 40 MSPS
Figure 31. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 40 MSPS
100 90 80
0
fIN = 10.3MHz fSAMPLE = 65MSPS
2V p-p, SFDR
-20
AIN1 AND AIN2 = -7dBFS SFDR = 74.76dBc IMD2 = 81.03dBc IMD3 = 75.00dBc
AMPLITUDE (dBFS)
05727-068
70
SNR/SFDR (dB)
-40
60 50 40 30 20 80dB REFERENCE
2V p-p, SNR
-60
-80
-100
05727-050
10 0 -60 -50 -40 -30 -20 -10 0
-120
0
2
4
6
8
10
12
14
16
18
20
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Figure 32. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 40 MSPS
Rev. B | Page 16 of 52
AD9228
0 AIN1 AND AIN2 = -7dBFS SFDR = 78.15dBc IMD2 = 77.84dBc IMD3 = 88.94dBc 90
-20
85 2V p-p, SFDR
AMPLITUDE (dBFS)
SINAD/SFDR (dB)
-40
80
-60
75
-80
70 2V p-p, SINAD
-100
05727-048
65
05727-072
-120
0
5
10
15
20
25
30
60 -40
-20
0
20
40
60
80
FREQUENCY (MHz)
TEMPERATURE (C)
Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 65 MSPS
Figure 36. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
0
-20
AIN1 AND AIN2 = -7dBFS SFDR = 76.75dBc IMD2 = 77.56dBc IMD3 = 77.01dBc
1.0 0.8 0.6 0.4
INL (LSB)
05727-051
AMPLITUDE (dBFS)
-40
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
05727-073
-60
-80
-100
-120
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 65 MSPS
Figure 37. INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
90 85 2V p-p, SFDR 80
SNR/SFDR (dB)
0.5 0.4 0.3 0.2
75 70 2V p-p, SNR 65 60
05727-071
DNL (LSB)
0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
05727-074
55 50
1
10
100
1000
FREQUENCY (MHz)
Figure 35. SNR/SFDR vs. Frequency, fSAMPLE = 65 MSPS
Figure 38. DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Rev. B | Page 17 of 52
AD9228
-45.0 0 NPR = 60.83dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz
-45.5
-20
AMPLITUDE (dBFS)
-46.0
CMRR (dB)
-40
-46.5
-60
-47.0
-80
-47.5
05727-075
-100
05727-076
-48.0 10
15
20
25
30
35
40
45
50
-120
0
5
10
15
20
25
30
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 39. CMRR vs. Frequency, fSAMPLE = 65 MSPS
Figure 41. Noise Power Ratio (NPR), fSAMPLE = 65 MSPS
1.2 0.26 LSB rms 1.0
0 -1
NUMBER OF HITS (Millions)
FUNDAMENTAL LEVEL (dB)
-2 -3 -4 -5 -6 -7 -8 -3dB CUTOFF = 315MHz
0.8
0.6
0.4
0.2
05727-086
-9 -10 0 50 100 150 200 250 300 350 400 450
0
N-3
N-2
N-1
N CODE
N+1
N+2
N+3
500
FREQUENCY (MHz)
Figure 40. Input-Referred Noise Histogram, fSAMPLE = 65 MSPS
Figure 42. Full-Power Bandwidth vs. Frequency, fSAMPLE = 65 MSPS
Rev. B | Page 18 of 52
05727-077
AD9228 THEORY OF OPERATION
The AD9228 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 12-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks. The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 43). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of lowQ inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article "Transformer-Coupled Front-End for Wideband A/D Converters" (Volume 39, April 2005) for more information. In general, the precise values depend on the application. The analog inputs of the AD9228 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 44 to Figure 47.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9228 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance.
H
CPAR
VIN + x S S
H
CSAMPLE
S S
CSAMPLE
VIN - x
CPAR
H
H
Figure 43. Switched-Capacitor Input Circuit
05727-006
Rev. B | Page 19 of 52
AD9228
90 SFDR (dBc) 85 80
90 85 80
SNR/SFDR (dB)
SFDR (dBc)
SNR/SFDR (dB)
75 SNR (dB) 70 65 60
05727-078
75 70 65 60
05727-100
SNR (dB)
55 50 0.2
55 50 0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.4
0.6
0.8
1.0
1.2
1.4
1.6
ANALOG INPUT COMMON-MODE VOLTAGE (V)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
Figure 44. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Figure 46. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, fSAMPLE = 40 MSPS
90 SFDR (dBc) 85 80
90 85 80
SNR/SFDR (dB)
SFDR (dBc)
SNR/SFDR (dB)
75 SNR (dB) 70 65 60
05727-079
75 70 65 60
05727-101
SNR (dB)
55 50 0.2
55 50 0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0.4
0.6
0.8
1.0
1.2
1.4
1.6
ANALOG INPUT COMMON-MODE VOLTAGE (V)
ANALOG INPUT COMMON-MODE VOLTAGE (V)
Figure 45. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz, fSAMPLE = 65 MSPS
Figure 47. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz, fSAMPLE = 40 MSPS
Rev. B | Page 20 of 52
AD9228
For best dynamic performance, the source impedances driving VIN + x and VIN - x should be matched such that commonmode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD - VREF) Span = 2 x (REFT - REFB) = 2 x VREF It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9228, the largest input span available is 2 V p-p.
ADT1-1WT 1:1 Z RATIO R C VIN + x
2V p-p
49.9 AVDD 1k 1k 0.1F
*CDIFF R C *CDIFF IS OPTIONAL
ADC AD9228
VIN - x AGND
Figure 48. Differential Transformer-Coupled Configuration for Baseband Applications
2V p-p 16nH 65 ADT1-1WT 0.1F 1:1 Z RATIO 16nH 499 16nH AVDD 1k 1k 0.1F
05727-047
33 VIN + x 2.2pF 33 1k
ADC AD9228
VIN - x
Figure 49. Differential Transformer-Coupled Configuration for IF Applications
Differential Input Configurations
There are several ways to drive the AD9228 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the AD8332 differential driver to drive the AD9228 provides excellent performance and a flexible interface to the ADC (see Figure 51) for baseband applications. This configuration is commonly used for medical ultrasound systems. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 48 and Figure 49), because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9228. Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed.
Single-Ended Input Configuration
A single-ended input may provide adequate performance in costsensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can be applied to the ADC's VIN + x pin while the VIN - x pin is terminated. Figure 50 details a typical singleended input configuration.
AVDD C R 2V p-p 49.9 0.1F AVDD 1k 25 0.1F 1k 1k *CDIFF R C *CDIFF IS OPTIONAL
05727-009
05727-007
VIN + x
ADC AD9228
VIN - x
Figure 50. Single-Ended Input Configuration
0.1F
LOP 0.1F 120nH 1V p-p 22pF
VIP VOH 187 680nH + 33
AVDD 10k VIN + x 1k
INH
AD8332
LNA LMD VOL LON VIN 187 680nH LPF VGA 68pF
10k AVDD 33 10k
ADC AD9228
VIN - x
0.1F
10k
18nF
274
0.1F
Figure 51. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter
Rev. B | Page 21 of 52
05727-008
AD9228
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9228 sample clock inputs (CLK+ and CLK-) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK- pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. Figure 52 shows a preferred method for clocking the AD9228. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-toback Schottky diodes across the secondary transformer limit clock excursions into the AD9228 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9228, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance.
Mini-Circuits(R) 0.1F CLK+ 50 ADT1-1WT, 1:1Z 0.1F XFMR 100 0.1F 0.1F SCHOTTKY DIODES: HSM2812
in parallel with a 39 k resistor (see Figure 55). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V and therefore offers several selections for the drive logic voltage.
0.1F
CLK+ CLK
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
CMOS DRIVER CLK OPTIONAL 100 CLK+
50*
0.1F
0.1F
ADC AD9228
CLK-
05727-027
0.1F
*50 RESISTOR IS OPTIONAL
39k
Figure 55. Single-Ended 1.8 V CMOS Sample Clock
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
CLK 50* CMOS DRIVER CLK 0.1F OPTIONAL 100 0.1F CLK+
0.1F CLK+
CLK+
*50 RESISTOR IS OPTIONAL
Figure 56. Single-Ended 3.3 V CMOS Sample Clock
Figure 52. Transformer-Coupled Differential Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9228 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9228. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. Jitter in the rising edge of the input is an important concern, and it is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz nominal. The loop has a time constant associated with it that must be considered in applications where the clock rate can change dynamically. This requires a wait time of 1.5 s to 5 s after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the period that the loop is not locked, the DCS loop is bypassed and the internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance.
Another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 53. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance.
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
CLK PECL DRIVER CLK 50* 240 240 100 0.1F
0.1F CLK+
0.1F CLK+
0.1F CLK- 50*
ADC AD9228
CLK-
05727-025
*50 RESISTORS ARE OPTIONAL
Figure 53. Differential PECL Sample Clock
AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515
CLK LVDS DRIVER CLK 50* 50* 100 0.1F
0.1F CLK+
0.1F CLK+
0.1F CLK-
ADC AD9228
CLK-
05727-026
*50 RESISTORS ARE OPTIONAL
Figure 54. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the CLK- pin should be bypassed to ground with a 0.1 F capacitor
Rev. B | Page 22 of 52
05727-028
CLK-
05727-024
ADC AD9228
0.1F
ADC AD9228
CLK-
AD9228
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by SNR Degradation = 20 x log 10(1/2 x x fA x tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 57). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9228. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators are the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock during the last step. Refer to the AN-501 Application Note and to the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs.
130 120 110 RMS CLOCK JITTER REQUIREMENT
200 AVDD CURRENT
CURRENT (mA)
Power Dissipation and Power-Down Mode
As shown in Figure 58 and Figure 59, the power dissipated by the AD9228 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers.
180 160 140 120 100 80 60 40 20 0 10 15 20 25 ENCODE (MSPS) 30 35 40 DRVDD CURRENT AVDD CURRENT 360 340 320 TOTAL POWER 300 280 260 240 220 200
05727-089
180
Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS
250 480 460 440 TOTAL POWER 150 420 400 380 360 50 340 DRVDD CURRENT 320 40 50 60
05727-081
CURRENT (mA)
100
16 BITS 14 BITS 12 BITS 10 BITS 0.125 ps 0.25 ps 0.5 ps 1.0 ps 2.0 ps 10 100 ANALOG INPUT FREQUENCY (MHz)
SNR (dB)
90 80 70 60 50 40 30 1
100
05727-038
0 10
20
30
300
1000
ENCODE (MSPS)
Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Figure 57. Ideal SNR vs. Input Frequency and Jitter
Rev. B | Page 23 of 52
POWER (mW)
POWER (mW)
AD9228
By asserting the PDWN pin high, the AD9228 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the SPI features are changed before the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset. The AD9228 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 F and 2.2 F decoupling capacitors on REFT and REFB, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors and approximately 375 s is required to restore full operation. There are several other power-down options available when using the SPI. The user can individually power down each channel or put the entire device into standby mode. The latter option allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features.
CH1 200mV/DIV = DCO CH2 200mV/DIV = DATA CH3 500mV/DIV = FCO 2.5ns/DIV
placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 60.
Figure 60. AD9228-65, LVDS Output Timing Example in ANSI-644 Mode (Default)
Digital Outputs and Timing
The AD9228 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SDIO/ODM pin or SPI. The LVDS standard can further reduce the overall power dissipation of the device by approximately 15 mW. See the SDIO/ODM Pin section or Table 16 in the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9228 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 termination resistor
An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 61. Figure 62 shows an example of trace lengths exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the user's responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all four outputs in order to drive longer trace lengths (see Figure 63). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. In addition, notice in Figure 63 that the histogram is improved compared with that shown in Figure 62. See the Memory Map section for more details.
Rev. B | Page 24 of 52
05727-045
AD9228
500 EYE: ALL BITS ULS: 10000/15600 400 EYE: ALL BITS ULS: 9599/15599
EYE DIAGRAM VOLTAGE (V)
EYE DIAGRAM VOLTAGE (V)
200
0
0
-200 -400
-500 -1ns -0.5ns 0ns 0.5ns 1ns
-1ns
-0.5ns
0ns
0.5ns
1ns
100
TIE JITTER HISTOGRAM (Hits)
100
TIE JITTER HISTOGRAM (Hits)
50
50
05727-043
0 -100ps
0ps
100ps
0 -150ps
-100ps
-50ps
0ps
50ps
100ps
150ps
Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Far Termination Only
200 ULS: 9600/15600 EYE: ALL BITS
Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Internal Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Far Termination Only
EYE DIAGRAM VOLTAGE (V)
The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. To change the output data format to twos complement, see the Memory Map section. Table 8. Digital Output Coding
Code 4095 2048 2047 0 (VIN + x) - (VIN - x), Input Span = 2 V p-p (V) +1.00 0.00 -0.000488 -1.00 Digital Output Offset Binary (D11 ... D0) 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000
0
-200 -1ns -0.5ns 0ns 0.5ns 1ns
100
TIE JITTER HISTOGRAM (Hits)
50
Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 12 bits times the sample clock rate, with a maximum of 780 Mbps (12 bits x 65 MSPS = 780 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up via the SPI to allow encode rates as low as 5 MSPS. See the Memory Map section for details on enabling this feature.
05727-044
0 -150ps
-100ps
-50ps
0ps
50ps
100ps
150ps
Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Far Termination Only
Rev. B | Page 25 of 52
05727-042
AD9228
Two output clocks are provided to assist in capturing data from the AD9228. The DCO is used to clock the output data and is equal to six times the sample clock (CLK) rate. Data is clocked out of the AD9228 and must be captured on the rising and Table 9. Flexible Output Test Modes
Output Test Mode Bit Sequence 0000 0001 Pattern Name Off (default) Midscale short Digital Output Word 1 N/A 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) N/A N/A 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) Register 0x19 to Register 0x1A 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) Digital Output Word 2 N/A Same Subject to Data Format Select N/A Yes
falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information.
0010
+Full-scale short
Same
Yes
0011
-Full-scale short
Same
Yes
0100
Checkerboard
0101 0110 0111
PN sequence long 1 PN sequence short1 One-/zero-word toggle
1000 1001
User input 1-/0-bit toggle
0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit) N/A N/A 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) Register 0x1B to Register 0x1C N/A
No
Yes Yes No
No No
1010
1x sync
N/A
No
1011
One bit high
N/A
No
1100
Mixed frequency
N/A
No
1
All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver.
Rev. B | Page 26 of 52
AD9228
When the SPI is used, the DCO phase can be adjusted in 60 increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO- timing, as shown in Figure 2, is 90 relative to the output data edge. An 8-, 10-, or 14-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility to lower and higher resolution systems. When changing the resolution to an 8- or 10-bit serial stream, the data stream is shortened. See Figure 3 for the 10-bit example. However, when using the 14-bit option, the data stream stuffs two 0s at the end of the 14-bit serial data. When the SPI is used, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. However, this can be inverted so that the LSB is first in the data output serial stream (see Figure 4). There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 - 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values). The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 - 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9228 inverts the bit stream with relation to the ITU standard. Table 10. PN Sequence
Sequence PN Sequence Short PN Sequence Long Initial Value 0x0df 0x29b80a First Three Output Samples (MSB First) 0xdf9, 0x353, 0x301 0x591, 0xfd7, 0x0a3
Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI.
SDIO/ODM Pin
The SDIO/ODM pin is for use in applications that do not require SPI mode operation. This pin can enable a low power, reduced signal option (similar to the IEEE 1596.3 reduced range link output standard) if it and the CSB pin are tied to AVDD during device power-up. This option should only be used when the digital output trace lengths are less than 2 inches from the LVDS receiver. When this option is used, the FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p, allowing the user to further reduce the power on the DRVDD supply. For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 k internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 k resistor in series with this pin to limit the current. Table 11. Output Driver Mode Pin Settings
Selected ODM Normal Operation ODM ODM Voltage 10 k to AGND AVDD Resulting Output Standard ANSI-644 (default) Low power, reduced signal option Resulting FCO and DCO ANSI-644 (default) Low power, reduced signal option
Rev. B | Page 27 of 52
AD9228
SCLK/DTP Pin
The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device powerup. When SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 1000 0000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 k resistor. This pin is both 1.8 V and 3.3 V tolerant. Table 12. Digital Test Pattern Pin Settings
Selected DTP Normal Operation DTP DTP Voltage 10 k to AGND AVDD Resulting D + x and D - x Normal operation 1000 0000 0000 Resulting FCO and DCO Normal operation Normal operation
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 k) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the AVDD current of the ADC to a nominal 232 mA at 65 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance.
Voltage Reference
A stable, accurate 0.5 V voltage reference is built into the AD9228. It is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. The VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to improve accuracy. When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9228. The recommended capacitor values and configurations for the AD9228 reference pin are shown in Figure 64. Table 13. Reference Settings
Selected Mode External Reference Internal, 2 V p-p FSR SENSE Voltage AVDD AGND to 0.2 V Resulting VREF (V) N/A 1.0 Resulting Differential Span (V p-p) 2 x external reference 2.0
Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section for information about the options available.
CSB Pin
The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant.
Rev. B | Page 28 of 52
AD9228
Internal Reference Operation
A comparator within the AD9228 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 64), setting VREF to 1 V. The REFT and REFB pins establish the input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage of the reference pin for either an internal or an external reference configuration. If the reference of the AD9228 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 66 depicts how the internal reference voltage is affected by loading.
VIN + x VIN - x REFT ADC CORE 0.1F 0.1F REFB VREF 1F 0.1F SELECT LOGIC SENSE 0.5V -30 0 0.5 1.0 1.5 2.0 2.5 3.0 0.1F
05727-083
External Reference Operation
The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 67 shows the typical drift characteristics of the internal reference in 1 V mode. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 k load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal 1.0 V.
5 0 -5
VREF ERROR (%)
-10 -15 -20 -25
+
2.2F
3.5
CURRENT LOAD (mA)
Figure 66. VREF Accuracy vs. Load
0.02
05727-010
0 -0.02 -0.04
Figure 64. Internal Reference Configuration
VIN + x VIN - x REFT ADC CORE 0.1F 0.1F REFB VREF 1F 0.1F AVDD SENSE SELECT LOGIC 0.5V 0.1F +
VREF ERROR (%)
-0.06 -0.08 -0.10 -0.12 -0.14 -0.16 -0.18 -40 -20 0 20 40 60 80
05727-084
2.2F
TEMPERATURE (C)
Figure 67. Typical VREF Drift
Figure 65. External Reference Operation
Rev. B | Page 29 of 52
05727-046
AD9228 SERIAL PORT INTERFACE (SPI)
The AD9228 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. There are three pins that define the SPI: SCLK, SDIO, and CSB (see Table 14). The SCLK pin is used to synchronize the read and write data presented to the ADC. The SDIO pin is a dualpurpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles. Table 14. Serial Port Pins
Pin SCLK SDIO Function Serial Clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles.
In addition to the operation modes, the SPI port configuration influences how the AD9228 operates. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins into their secondary modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin sections. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, the user should ensure that the serial port remains synchronized with the CSB line when using this mode. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
CSB
HARDWARE INTERFACE
The pins described in Table 14 compose the physical interface between the user's programming device and the serial port of the AD9228. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Assuming the same load for each AD9228, Figure 68 shows the number of SDIO pins that can be connected together and the resulting VOH level. This interface is flexible enough to be controlled by either serial PROMS or PIC mirocontrollers, providing the user with an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note).
The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 69 and Table 15. During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to obtain instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring additional instructions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction.
Rev. B | Page 30 of 52
AD9228
1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715
If the user chooses not to use the SPI, these dual-function pins serve their secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pin-strappable functions are supported on the SPI pins. For users who wish to operate the ADC without using the SPI, remove any connections from the CSB, SCLK/DTP, and SDIO/ODM pins. By disconnecting these pins from the control bus, the ADC can function in its most basic operation. Each of these pins has an internal termination that floats to its respective level.
0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER
05727-102
VOH (V)
Figure 68. SDIO Pin Loading
tDS tS
CSB
tHI tDH tLO
tCLK
tH
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON'T CARE
Figure 69. Serial Timing Details
Table 15. Serial Timing Definitions
Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO tDIS_SDIO Timing (Minimum, ns) 5 2 40 5 2 16 16 10 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 69) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 69)
Rev. B | Page 31 of 52
05727-012
AD9228 MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x05 and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22). The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The (MSB) Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 of this address followed by a 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
When the AD9228 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: "Bit is set" is synonymous with "bit is set to Logic 1" or "writing Logic 1 for the bit." Similarly, "clear a bit" is synonymous with "bit is set to Logic 0" or "writing Logic 0 for the bit."
Rev. B | Page 32 of 52
AD9228
Table 16. Memory Map Register
Addr. (MSB) (Hex) Bit 7 Register Name Chip Configuration Registers 00 chip_port_config 0 Bit 6 LSB first 1 = on 0 = off (default) Bit 5 Soft reset 1 = on 0 = off (default) Bit 4 1 Bit 3 1 Bit 2 Soft reset 1 = on 0 = off (default) Bit 1 LSB first 1 = on 0 = off (default) (LSB) Bit 0 0 Default Value (Hex) 0x18 Default Notes/ Comments The nibbles should be mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a readonly register. Child ID used to differentiate graded devices.
01
chip_id
8-bit Chip ID Bits [7:0] (AD9228 = 0x02), (default)
0x02
02
chip_grade
X
Child ID [6:4] (identify device variants of Chip ID) 000 = 65 MSPS 001 = 40 MSPS X Clock Channel DCO 1 = on 0 = off (default) X Clock Channel FCO 1 = on 0 = off (default) X
X
X
X
X
Read only
Device Index and Transfer Registers 05 device_index_A X
FF
device_update
X
X
Data Channel D 1 = on (default) 0 = off X
Data Channel C 1 = on (default) 0 = off X
Data Channel B 1 = on (default) 0 = off X
Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default)
0x0F
Bits are set to determine which on-chip device receives the next write command. Synchronously transfers data from the master shift register to the slave. Determines various generic modes of chip operation. Turns the internal duty cycle stabilizer on and off.
0x00
ADC Functions 08 modes
X
X
X
X
X
09
clock
X
X
X
X
X
Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset X X Duty cycle stabilizer 1 = on (default) 0 = off
0x00
0x01
0D
test_io
User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once
Reset PN long gen 1 = on 0 = off (default)
Reset PN short gen 1 = on 0 = off (default)
Output test mode--see Table 9 in the Digital Outputs and Timing section 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = -FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1x sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode)
0x00
When this register is set, the test data is placed on the output pins in place of normal data.
Rev. B | Page 33 of 52
AD9228
Addr. (Hex) 14 Register Name output_mode (MSB) Bit 7 X Bit 6 0 = LVDS ANSI-644 (default) 1 = LVDS low power (IEEE 1596.3 similar) X Bit 5 X Bit 4 X Bit 3 X Bit 2 Output invert 1 = on 0 = off (default) (LSB) Bit 0 Bit 1 00 = offset binary (default) 01 = twos complement Default Value (Hex) 0x00 Default Notes/ Comments Configures the outputs and the format of the data.
15
output_adjust
X
Output driver termination 00 = none (default) 01 = 200 10 = 100 11 = 100
X
X
X
X
0x00
16
output_phase
X
X
X
X
19 1A 1B 1C 21
user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb serial_control
B7 B15 B7 B15 LSB first 1 = on 0 = off (default)
B6 B14 B6 B14 X
B5 B13 B5 B13 X
B4 B12 B4 B12 X
0011 = output clock phase adjust (0000 through 1010) 0000 = 0 relative to data edge 0001 = 60 relative to data edge 0010 = 120 relative to data edge 0011 = 180 relative to data edge (default) 0100 = 240 relative to data edge 0101 = 300 relative to data edge 0110 = 360 relative to data edge 0111 = 420 relative to data edge 1000 = 480 relative to data edge 1001 = 540 relative to data edge 1010 = 600 relative to data edge 1011 to 1111 = 660 relative to data edge B3 B2 B1 B0 B11 B3 B11 <10 MSPS, low encode rate mode 1 = on 0 = off (default) X B10 B2 B10 B9 B1 B9 B8 B0 B8
0x03
Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor. On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected.
0x00 0x00 0x00 0x00 0x00
000 = 12 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits
User-defined pattern, 1 LSB. User-defined pattern, 1 MSB. User-defined pattern, 2 LSB. User-defined pattern, 2 MSB. Serial stream control. Default causes MSB first and the native bit stream (global).
22
serial_ch_stat
X
X
X
X
X
Channel output reset 1 = on 0 = off (default)
Channel powerdown 1 = on 0 = off (default)
0x00
Used to power down individual sections of a converter (local).
Rev. B | Page 34 of 52
AD9228
Power and Ground Recommendations
When connecting power to the AD9228, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts, with minimal trace lengths. A single PC board ground plane should be sufficient when using the AD9228. With proper decoupling and smart partitioning of the PC board's analog, digital, and clock sections, optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9228. An exposed continuous copper plane on the PCB should mate to the AD9228 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 70 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
SILKSCREEN PARTITION PIN 1 INDICATOR
Figure 70. Typical PCB Layout
Rev. B | Page 35 of 52
05727-013
AD9228 EVALUATION BOARD
The AD9228 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using a transformer (default) or an AD8332 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the drive circuitry of the AD8332. Each input configuration can be selected by changing the connection of various jumpers (see Figure 73 to Figure 77). Figure 71 shows the typical bench characterization setup used to evaluate the ac performance of the AD9228. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. See Figure 73 to Figure 81 for the complete schematics and layout diagrams demonstrating the routing and grounding techniques that should be applied at the system level. each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is needed in addition to the other supplies.
INPUT SIGNALS
When connecting the clock and analog sources to the evaluation board, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644B signal generators or the equivalent, as well as a 1 m, shielded, RG-58, 50 coaxial cable. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most Analog Devices evaluation boards can accept approximately 2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 terminations. Good choices of such band-pass filters are available from TTE, Allen Avionics, and K&L Microwave, Inc. The filter should be connected directly to the evaluation board if possible.
POWER SUPPLIES
This evaluation board has a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end of the supply is a 2.1 mm inner diameter jack that connects to the PCB at P503. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. When operating the evaluation board in a nondefault condition, L504 to L507 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P501 to connect a different supply for
OUTPUT SIGNALS
The default setup uses the Analog Devices, Inc., HSC-ADCFPGA-4/HSC-ADC-FPGA-8 high speed deserialization board to deserialize the digital output data and convert it to parallel CMOS. These two channels interface directly with the Analog Devices standard dual-channel FIFO data capture board (HSCADC-EVALB-DC). Two of the four channels can then be evaluated at the same time. For more information on the channel settings and optional settings of these boards, visit www.analog.com/FIFO.
WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz 6V DC 2A MAX SWITCHING POWER SUPPLY - 5.0V + - 1.8V + 1.8V - + - 3.3V + - 3.3V + - 1.5V + - 3.3V +
1.5V_FPGA
GND
GND
GND
GND
GND
GND
AVDD_5V
DRVDD_DUT
AVDD_3.3V
AVDD_DUT
3.3V_D
GND
VCC
ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER
BAND-PASS FILTER
XFMR INPUT
AD9228
EVALUATION BOARD CH A TO CH D 12-BIT SERIAL LVDS SPI
CLK
SPI
SPI
Figure 71. Evaluation Board Connection
Rev. B | Page 36 of 52
05727-014
HSC-ADC-FPGA-4/ HSC-ADC-FPGA-8 HIGH SPEED DESERIALIZATION BOARD 2 CH 12-BIT PARALLEL CMOS SPI
HSC-ADC-EVALB-DC FIFO DATA CAPTURE BOARD USB CONNECTION
PC RUNNING ADC ANALYZER AND SPI USER SOFTWARE
AD9228
DEFAULT OPERATION AND JUMPER SELECTION SETTINGS
The following is a list of the default and optional settings or modes allowed on the AD9228 Rev. A evaluation board. * POWER: Connect the switching power supply that is provided with the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P503. AIN: The evaluation board is set up for a transformercoupled analog input with an optimum 50 impedance match of 200 MHz of bandwidth (see Figure 72). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2.
0 -2 -4
*
A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U202). Populate R225 and R227 with 0 resistors and remove R217 and R218 to disconnect the default clock path inputs. In addition, populate C207 and C208 with a 0.1 F capacitor and remove C210 and C211 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options. In addition, an on-board oscillator is available on the OSC201 and can act as the primary clock source. The setup is quick and involves installing R212 with a 0 resistor and setting the enable jumper (J205) to the on position. If the user wishes to employ a different oscillator, two oscillator footprint options are available (OSC201) to check the ADC performance. * PDWN: To enable the power-down feature, short J201 to AVDD on the PDWN pin. SCLK/DTP: To enable the digital test pattern on the digital outputs of the ADC, use J204. If J204 is tied to AVDD during device power-up, Test Pattern 1000 0000 0000 is enabled. See the SCLK/DTP Pin section for details. SDIO/ODM: To enable the low power, reduced signal option (similar to the IEEE 1595.3 reduced range link LVDS output standard), use J203. If J203 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI-644 standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, reducing the power of the DRVDD supply. See the SDIO/ODM Pin section for more details. CSB: To enable processing of the SPI information on the SDIO and SCLK pins, tie J202 low in the always enable mode. To ignore the SDIO and SCLK information, tie J202 to AVDD. Non-SPI Mode: For users who wish to operate the DUT without using SPI, remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. D + x, D - x: If an alternative data capture method to the setup shown in Figure 73 is used, optional receiver terminations, R206 to R211, can be installed next to the high speed backplane connector.
-3dB CUTOFF = 200MHz
*
AMPLITUDE (dBFS)
-6 -8 -10 -12
05727-088
*
-14 -16
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 72. Evaluation Board Full-Power Bandwidth
*
VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R237. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 or ADR520 is also included on the evaluation board. Populate R231 and R235 and remove C214. Proper use of the VREF options is noted in the Voltage Reference section. RBIAS: RBIAS has a default setting of 10 k (R201) to ground and is used to set the ADC core bias current. CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input is 50 terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs.
*
*
* *
*
Rev. B | Page 37 of 52
AD9228
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION
The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 17. For more details on the AD8332 dual VGA, including how it works and its optional pin settings, consult the AD8332 data sheet. To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. * Remove R102, R115, R128, R141, R161, R162, R163, R164, T101, T102, T103, and T104 in the default analog input path. * * Populate R101, R114, R127, and R140 with 0 resistors in the analog input path. Populate R105, R113, R118, R124, R131, R137, R151, and R160 with 0 resistors in the analog input path to connect the AD8332. Populate R152, R153, R154, R155, R156, R157, R158, R159, C103, C105, C110, C112, C117, C119, C124, and C126 with 10 k resistors to provide an input common-mode level to the ADC analog inputs. Remove R305, R306, R313, R314, R405, R406, R412, and R424 to configure the AD8332.
*
*
In this configuration, L301 to L308 and L401 to L408 are populated with 0 resistors to allow signal connection and use of a filter if additional requirements are necessary.
Rev. B | Page 38 of 52
AD9228
AVDD_DUT R105 DNP FB102 R108 10 33 R106 DNP CM1
2 3 5 4
CH_A P102 VGA INPUT CONNECTION DNP INH1 AIN CHANNEL A R101 P101 DNP AIN R102 64.9 R103 0 R104 0 C101 0.1F
R152 DNP
T101
1 6
VIN_A R161 499 C103 DNP C104 2.2pF R109 1k VIN_A FB103 R110 10 33 C105 DNP R156 DNP
CM1 R107 DNP
R113 FB101 DNP 10 C102 0.1F CH_A CM1 E101
AVDD_DUT
R111 1k R112 1k
C107 0.1F
C106 DNP
AVDD_DUT AVDD_DUT
VGA INPUT CONNECTION INH2 CHANNEL B R114 P103 DNP AIN R115 64.9 P104 DNP AIN R117 0
CH_B
R118 DNP FB105 R121 10 33 R119 DNP
R153 DNP
T102
1 6
FB104 10 C108 0.1F CM2 R116 0
VIN_B R162 499 C110 DNP C111 2.2pF R123 1k VIN_B FB106 R122 10 33 C112 DNP R157 DNP
2 3
5 4
CM2 R120 DNP
R124 C109 DNP 0.1F CH_B CM2 E102
AVDD_DUT
R125 1k R126 1k
C114 0.1F
C113 DNP AVDD_DUT R154 DNP
AVDD_DUT
CH_C P106 VGA INPUT CONNECTION DNP INH3 AIN CHANNEL C R127 P105 DNP AIN R128 64.9 R129 0 R130 0 C115 0.1F
R131 DNP FB108 R134 10 33 R132 DNP
T103
1 6
VIN_C R163 499 C117 DNP C118 2.2pF R135 1k VIN_C R158 DNP
CM3
2 3
5 4
CM3 R133 DNP
R137 FB107 DNP 10 C116 0.1F CH_C CM3 E103
FB109 R136 10 33 C120 DNP
C119 DNP
AVDD_DUT
R138 1k R139 1k
C121 0.1F
AVDD_DUT AVDD_DUT
VGA INPUT CONNECTION INH4 CHANNEL D R140 P107 DNP AIN R141 64.9 P108 DNP AIN R142 0
CH_D
R151 DNP FB111 R146 10 33 R144 DNP
5 4
R155 DNP
T104
1 6
FB110 C122 10 0.1F 2 CM4
3
VIN_D R164 499 C124 DNP C125 2.2pF R148 1k VIN_D FB112 R147 33 10 C126 DNP R159 DNP
CM4 R145 DNP
R160 R143 DNP 0 C123 0.1F CH_D CM4 E104
AVDD_DUT
DNP: DO NOT POPULATE
Figure 73. Evaluation Board Schematic, DUT Analog Inputs
Rev. B | Page 39 of 52
05727-015
R149 1k R150 1k
C128 0.1F
C127 DNP
AVDD_DUT
REFERENCE CIRCUIT OPTIONAL EXT REF AVDD_DUT R229 4.99k R231 DNP R234 DNP DNP VREF = 0.5V VREF = EXTERNAL
DCO FCO CHA CHB CHC R202 100k 1 J201 3 CHD
AD9228
C204 0.1F
REFERENCE DECOUPLING
VREF_DUT
VREF SELECT VSENSE_DUT
DIGITAL OUTPUTS
V-
U203 ADR510/20 1V TRIM/NC V+ DNP DNP DNP VREF = 0.5V(1+R232/R233) VREF = 1V C212 0.1F C213 0.1F R233 DNP R237 0 C214 1F R236 DNP R230 10k
50 49 48 47 46 45 44 53 33 R246 DNP R248 DNP R250 DNP R252 DNP R254 DNP R251 0 R253 0 R255 0 R249 0 R247 0 AVDD_3.3V S6 AVDD_3.3V S7 R256 DNP R258 DNP R260 DNP AVDD_3.3V S8 AVDD_3.3V S9 R262 DNP R264 DNP AVDD_3.3V S10 R257 0 R259 0 R261 0 R263 0 R265 0 C3 D3 43 GNDCD2 52 32 C2 GNDCD1 D2 42
AVDD_DUT
C202 2.2F
C203 0.1F
R232 DNP R235 DNP
R201 10k R228 470k
DCO R206 DNP R207 FCO DNP CHA R208 DNP CHB R209 DNP CHC R210 DNP CHD R211 DNP
CW
AVDD_DUT AVDD_DUT
VIN_C VIN_C
VREF_DUT VSENSE_DUT AVDD_DUT VIN_B VIN_B
C201 0.1F
U201
VIN - C VIN + C AVDD AVDD REFT REFB VREF SENSE RBIAS AVDD VIN + B VIN - B
48 47 46 45 44 43 42 41 40 39 38 37
AVDD_DUT REMOVE C214 WHEN USING EXTERNAL VREF
PWDN ENABLE ALWAYS ENABLE SPI
AVDD_3.3V S0 R244 DNP R245 0
2
AVDD_DUT AVDD_DUT VIN_A VIN_A AVDD_DUT
R266 100k - DNP
R267 100k - DNP
AD9228LFCSP
AVDD AVDD VIN - A VIN + A AVDD PDWN 1 3 J202
P202 GNDCD10 60 D10 C10 GNDCD9 40 59 D9 C9 39 GNDCD8 58 D8 C8 38 GNDCD7 57 D7 C7 37 GNDCD6 56 D6 C6 36 GNDCD5 55 D5 C5 35 GNDCD4 54 D4 C4 34 GNDCD3
2
ODM ENABLE AVDD_3.3V DTP ENABLE S1 AVDD_3.3V S2
CSB_DUT
D-D D+D D-C D+C D-B D+B D-A D+A FCO- FCO+ DCO- DCO+
R203 100k
R204 100k
R205 10k
AVDD_DUT AVDD_DUT VIN_D VIN_D AVDD_DUT AVDD_DUT CLK CLK AVDD_DUT AVDD_DUT GND DRVDD_DUT
CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD
1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25
AVDD AVDD VIN - D VIN + D AVDD AVDD CLK- CLK+ AVDD AVDD DRGND DRVDD
AVDD_DUT GND DRVDD_DUT
J203 1 3 SDIO_ODM J204 3 1 SCLK_DTP
2
2
13 14 15 16 17 18 19 20 21 22 23 24
51 D1 41 C1 31 GNDAB10 30 C10 B10 20 10 GNDAB9 29 9 28 8 27 7 26 6 25 SCLK_CHB SDI_CHB 5 24 A9 A8 A7 A6 A5 A4 B9
GNDAB8
CHD CHD
CHC CHC CHB
CHB CHA CHA FCO FCO
DCO DCO
AVDD_3.3V S3 AVDD_3.3V S4 AVDD_3.3V S5
19 B8
GNDAB7
VS 1
GND 31
ENCODE INPUT
1 3 5 7 R220 DNP R221 10k U202
33
RSET 32
6 7 8 9 10 11 12 13 14 15 16 25
ENC E201 1
R238 DNP
R239 10k
VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
ENC DNP 2 5
T201 3 4
CR201 HSMS2812
3
2
R216 0
C216 0.1F
R218 0 C206 0.1F R224 0
1
6
1
05727-016
Figure 74. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
AVDD_3.3V J205 OPTIONAL CLOCK DRIVE CIRCUIT R222 4.12k AVDD_3.3V C207 0.1F DNP CLK 23 22 R240 243 19 18 R241 243 1 R243 100 CLK C210 0.1F C209 0.1F DNP E202 LVDS OUTPUT 1 E203 C215 0.1F DNP CLIP SINE OUT (DEFAULT) CLK C217 0.1F C218 0.1F C219 0.1F C220 0.1F C221 0.1F AVDD_3.3V R242 100 C208 0.1F DNP LVPECL OUTPUT CLK SDO_CHB CSB3__CHB CSB4_CHB 4 23 3 22 2 21 1 A3 A2 A1
Rev. B | Page 40 of 52
R225 0 DNP
OPT_CLK
18 B7
GNDAB6
AVDD_3.3V
C224 0.1F
17
GNDAB5
R214 10k
B6
16
GNDAB4
3
OPTIONAL CLOCK OSCILLATOR
AVDD_3.3V
ENABLE
B5 B4
GNDAB3
15 14
GNDAB2
SCLK_CHA SDI_CHA B3 B2
GNDAB1
2
1
R226 49.9 DNP
DISABLE R219 R215 DNP 10k OPT_CLK
13 12 B1 11
CSB1_CHA CSB2_CHA SDO_CHA
OSC201 14 VCC OE 12 VCC' OE' 10 OUT' GND' 8 OUT GND VFAC3H-L R212 0 DNP
P201
OPT_CLK
R227 0 DNP
GND_PAD 2 CLK OUT0 3 OUT0B CLKB AD9515 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 5 SYNCB OUT1 SIGNAL=DNC;27,28 OUT1B
NC = NO CONNECT
HEADER 6469169-1
CLOCK CIRCUIT
R213 49.9k
C205 0.1F
R205-R211 OPTIONAL OUTPUT TERMINATIONS
P203
OPT_CLK
R217 0
R223 0
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
C222 0.1F
C223 0.1F
DNP: DO NOT POPULATE
C211 0.1F
AD9228
POPULATE L301-L308 WITH 0 RESISTORS OR DESIGN YOUR OWN FILTER.
CH_D
CH_D
CH_C
R301 DNP C301 L301 DNP 0 C303 L305 DNP 0 R303 DNP C305 0.1F R305 374 R307 187 U301 25 26 27 28 29 30 31 32 ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 R308 187
R302 DNP C302 L302 L303 DNP L304 0 0 0 C304 DNP L308 0 R304 DNP C308 0.1F C309 1000pF R310 187
CH_C
EXTERNAL VARIABLE GAIN DRIVE VG VARIABLE GAIN CIRCUIT (0-1.0V DC) VG GND CW AVDD_5V R320 R319 39k 10k
1 2
JP301
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL C AND CHANNEL D
POWER DOWN ENABLE (0-1V = DISABLE POWER)
L306 L307 0 0
AVDD_5V
R306 374 R309 187
AVDD_5V
VOL1 VPSV
R313 10k DNP
VOL2 VOH2 COMM
COMM VOH1
NC
R312 10k
AVDD_5V
C310 0.1F
R311 10k DNP
AD8332
LON1 VPS1 INH1
LMD1 LMD2
C312 0.1F
INH2 VPS2 LON2
C311 0.1F
C313 0.1F
C314 0.1F
R315 10k
C315 10F
C316 0.1F
R316 274 C317 0.018F
C320 0.1F
C321 0.1F
R317 274 C322 0.018F
C325 0.1F
C326 10F
R318 10k
C318 22pF L309 120nH C319 0.1F
C323 22pF L310 120nH C324 0.1F INH3
DNP: DO NOT POPULATE
INH4
Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit
Rev. B | Page 41 of 52
05727-017
MODE PIN POSITIVE GAIN SLOPE = 0-1.0V NEGATIVE GAIN SLOPE = 2.25V-5.0V
HILO PIN HI GAIN RANGE = 2.25V-5.0V LO GAIN RANGE = 0-1.0V
RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2
16 15 14 13 12 11 10 9
VG
R314 10k DNP
1 2 3
4 5
AVDD_5V
AVDD_5V
6 7 8
RCLAMP PIN HILO PIN = LO = 50mV HILO PIN = H = 75mV
C306 C307 0.1F 0.1F
24 23
22 21
20
19 18 17
AD9228
CH_B
CH_B
CH_A
R401 DNP C401 L401 DNP 0 SPI CIRCUITRY FROM FIFO +5V = PROGRAMMING = AVDD_5V +3.3V = NORMAL OPERATION = AVDD_3.3V AVDD_3.3V AVDD_5V J402 C427 0.1F U402 1 VDD 2 GP5 3 GP4 4 R422 0-DNP 8 VSS 7 GP0 6 GP1 R421 0-DNP C402 L402 L403 DNP L404 0 0 0
R402 DNP
POWER DOWN ENABLE (0-1V = DISABLE POWER)
POPULATE L401-L408 WITH 0 RESISTORS OR DESIGN YOUR OWN FILTER.
C403 L405 DNP 0 R403 DNP L406 L407 0 0
C404 DNP L408 0 R404 DNP
CH_A
CSB1_CHA
SCLK_CHA
SDI_CHA
C405 0.1F
C406 C407 0.1F 0.1F
R407 187 R410 187
R408 187
AVDD_5V
R409 187
C412 0.1F
R426 0
R428 0
R420 0
R427 0
R405 374 C411 1000pF R413 10k DNP
R406 374
C408 0.1F
SDO_CHA
REMOVE WHEN USING OR PROGRAMMING PIC (U402)
AVDD_3.3V
24 23
22 21
20
AVDD_5V
NC
AVDD_5V RCLAMP PIN HILO PIN = LO = 50mV HILO PIN = H = 75mV
R411 10k
U401
19 18 17
R433 1k
COMM VOH1
VOL1 VPSV
VOL2 VOH2 COMM
R412 10k DNP VG
RESET/REPROGRAM
R424 10k DNP
1 2 3 4 MCLR/ GP2 5 GP3 PIC12F629 R419 261 CR401
R418 4.75k
S401
R423 0-DNP
SDIO_ODM AVDD_DUT R431 1k R425 10k 2 GND 3 A2 VCC 5 Y2 4 AVDD_DUT
OPTIONAL
LON1 VPS1 INH1
LMD1 LMD2
1 2 3
4 5
C410 0.1F
6 7 8
INH2 VPS2 LON2
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL A AND CHANNEL B
HILO PIN HI GAIN RANGE = 2.25V-5.0V LO GAIN RANGE = 0-1.0V
AVDD_5V
AVDD_5V
MODE PIN POSITIVE GAIN SLOPE = 0-1.0V NEGATIVE GAIN SLOPE = 2.25V-5.0V
R416 C420 0.018F 274
Figure 76. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued)
AD8332 C423 0.1F RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2 16 15 14 13 12 11 10 9 C424 0.1F R432 NC7WZ07 1k 1 A1 Y1 6
Rev. B | Page 42 of 52
E401 R415 274 C416 0.1F C417 0.1F C425 0.1F C426 R417 10F 10k
C409 0.1F
25 26 27 28 29 30 31 32
ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1
U403
C429 0.1F
MCLR/GP3 7 8 9 10
J401 PICVCC 1 2 GP1 3 4 GP0 5 6
R414 10k
C413 10F
C414 0.1F
C415 0.018F
NC7WZ16 1 A1 Y1 6 2 GND 3 A2 R430 10k R429 10k VCC 5 Y2 4
SCLK_DTP AVDD_DUT CSB_DUT
GP1 GP0
PICVCC
MCLR/GP3
PIC PROGRAMMING HEADER
C418 22pF L409 120nH L410 120nH C422 0.1F C419 0.1F
C421 22pF
U404
C428 0.1F
05727-018
INH2
INH1
DNP: DO NOT POPULATE
POWER SUPPLY INPUT 6V, 2V MAXIMUM F501 FER501 1 4 3 CHOKE_COIL CR501 R501 261 2 PWR_IN SMDC110F + 2 3 C501 10F D501 S2A_RECT 2A DO-214AA P503 1
D502 3A SHOT_RECT DO-214AB
OPTIONAL POWER INPUT P501 P1 1 5V_AVDD AVDD_5V +5.0V C518 0.1F C519 0.1F C502 10F C503 0.1F L502 10H AVDD_DUT C504 10F C505 0.1F L508 10H AVDD_3.3V C508 10F C509 0.1F +3.3V AVDD_3.3V C524 0.1F C525 0.1F C526 0.1F +1.8V AVDD_DUT C527 0.1F C528 0.1F AVDD_5V C520 0.1F DUT_AVDD 3.3V_AVDD DUT_DRVDD P2 2 P3 3 P4 4 P5 5 P6 6 P7 7 P8 8 L503 10H
DECOUPLING CAPACITORS
C521 0.1F
C522 0.1F
C523 0.1F
C529 0.1F
C530 0.1F
C531 0.1F
GND
C514 1F
1
U503 PWR_IN INPUT
GND
U504 L504 10H DUT_DRVDD C513 1F PWR_IN C534 1F 3 ADP3339AKC-5
GND
3
ADP3339AKC-1.8
1
C515 1F
C532 1F
GND
1
05727-019
AD9228
DNP: DO NOT POPULATE
1
Figure 77. Evaluation Board Schematic, Power Supply Inputs
Rev. B | Page 43 of 52
L501 10H DRVDD_DUT +1.8V DRVDD_DUT C506 10F C507 0.1F U501 PWR_IN INPUT OUTPUT4 4 3 OUTPUT1 ADP3339AKC-1.8 2 L505 10H DUT_AVDD PWR_IN 3 C512 1F 2 OUTPUT1 4 OUTPUT4
H1
H3
C516 0.1F
C517 0.1F
H2
H4 MOUNTING HOLES CONNECTED TO GROUND
U502 ADP3339AKC-3.3 INPUT OUTPUT1 2 OUTPUT4 4
L506 10H 3.3V_AVDD C533 1F
INPUT
OUTPUT1
2 OUTPUT4 4
L507 10H 5V_AVDD C535 1F
AD9228
Figure 78. Evaluation Board Layout, Primary Side
Rev. B | Page 44 of 52
05727-020
AD9228
Figure 79. Evaluation Board Layout, Ground Plane
Rev. B | Page 45 of 52
05727-021
AD9228
Figure 80. Evaluation Board Layout, Power Plane
Rev. B | Page 46 of 52
05727-022
AD9228
Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. B | Page 47 of 52
05727-023
AD9228
Table 17. Evaluation Board Bill of Materials (BOM) 1
Item 1 2 Qty. 1 75 Reference Designator AD9228LFCSP_REVA C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, C218, C219, C220, C221, C222, C223, C224, C310, C311, C312, C313, C314, C316, C319, C320, C321, C324, C325, C409, C410, C412, C414, C416, C417, C419, C422, C423, C424, C425, C427, C428, C429, C503, C505, C507, C509, C516, C517, C518, C519, C520, C521, C522, C523, C524, C525, C526, C527, C528, C529, C530, C531 C104, C111, C118, C125 C315, C326, C413, C426 C202 C309, C411 C317, C322, C415, C420 C318, C323, C418, C421 C501 C214, C512, C513, C514, C515, C532, C533, C534, C535 C305, C306, C307, C308, C405, C406, C407, C408 C502, C504, C506, C508 CR201 CR401, CR501 D502 D501 Device PCB Capacitor Package PCB 402 Value PCB 0.1 F, ceramic, X5R, 10 V, 10% tol Manufacturer Murata Manufacturer's Part Number GRM155R71C104KA88D
3
4
Capacitor
402
4 5 6 7 8 9 10
4 1 2 4 4 1 9
Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor
805 603 402 402 402 1206 603
2.2 pF, ceramic, COG, 0.25 pF tol, 50 V 10 F, 6.3 V 10% ceramic, X5R 2.2 F, ceramic, X5R, 6.3 V, 10% tol 1000 pF, ceramic, X7R, 25 V, 10% tol 0.018 F, ceramic, X7R, 16 V, 10% tol 22 pF, ceramic, NPO, 5% tol, 50 V 10 F, tantalum, 16 V, 20% tol 1 F, ceramic, X5R, 6.3 V, 10% tol 0.1 F, ceramic, X7R, 50 V, 10% tol 10 F, ceramic, X5R, 6.3 V, 20% tol 30 V, 20 mA, dual Schottky Green, 4 V, 5 m candela 3 A, 30 V, SMC 2 A, 50 V, SMC
Murata
GRM1555C1H2R2GZ01B
Murata Murata Murata AVX Murata Rohm Murata
GRM219R60J106KE19D GRM188C70J225KE20D GRM155R71H102KA01D 0402YC183KAT2A GRM1555C1H220JZ01D TCA1C106M8R GRM188R61C105KA93D
11
8
Capacitor
805
Murata
GRM21BR71H104KA01L
12 13 14 15 16
4 1 2 1 1
Capacitor Diode LED Diode Diode
603 SOT-23 603 DO-214AB DO-214AA
Murata Agilent Technologies Panasonic Micro Commercial Co. Micro Commercial Co.
GRM188R60J106M HSMS2812-TRIG LNJ314G8TRA SK33-TP S2A-TP
Rev. B | Page 48 of 52
AD9228
Item 17 Qty. 1 Reference Designator F501 Device Fuse Package 1210 Value 6.0 V, 2.2 A tripcurrent resettable fuse 10 H, 5 A, 50 V, 190 @ 100 MHz 10 , test freq 100 MHz, 25% tol, 500 mA 100 mil header jumper, 2-pin 100 mil header jumper, 3-pin 100 mil header male, 4 x 3 triple row straight 100 mil header, male, 2 x 5 double row straight 10 H, bead core 3.2 x 2.5 x 1.6 SMD, 2 A 120 nH, test freq 100 MHz, 5% tol, 150 mA 0 , 1/8 W, 5% tol Manufacturer Tyco/Raychem Manufacturer's Part Number NANOSMDC110F-2
18 19
1 12
FER501 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 JP301 J205, J402 J201 to J204
Choke coil Ferrite bead
2020 603
Murata Murata
DLW5BSN191SQ2L BLM18BA100SN1B
20 21 22
1 2 1
Connector Connector Connector
2-pin 3-pin 12-pin
Samtec Samtec Samtec
TSW-102-07-G-S TSW-103-07-G-S TSW-104-08-G-T
23
1
J401
Connector
10-pin
Samtec
TSW-105-08-G-D
24
8
L501, L502, L503, L504, L505, L506, L507, L508 L309, L310, L409, L410
Ferrite bead
1210
Murata
BLM31PG500SN1L
25
4
Inductor
402
Murata
LQG15HNR12J02B
26
16
27 28
1 5
L301, L302, L303, L304, L305, L306, L307, L308, L401, L402, L403, L404, L405, L406, L407, L408 OSC201 P101, P103, P105, P107, P201 P202
Resistor
805
NIC Components
NRC10ZOTRF
Oscillator Connector
SMT SMA
29
1
Connector
Header
30 31
1 15
P503 R201, R205, R214, R215, R221, R239, R312, R315, R318, R411, R414, R417, R425, R429, R430 R103, R117, R129, R142, R216, R217, R218, R223, R224, R237, R420, R426, R427, R428 R102, R115, R128, R141 R104, R116, R130, R143
Connector Resistor
0.1", PCMT 402
Clock oscillator, 65.00 MHz, 3.3 V Side-mount SMA for 0.063" board thickness 1469169-1, right angle 2-pair, 25 mm, header assembly SC1153, power supply connector 10 k, 1/16 W, 5% tol
Valpey Fisher Johnson Components Tyco
VFAC3H-L-65MHz 142-0710-851
6469169-1
Switchcraft NIC Components
RAPC722X NRC04J103TRF
32
14
Resistor
402
0 , 1/16 W, 5% tol
NIC Components
NRC04Z0TRF
33 34
4 4
Resistor Resistor
402 603
64.9 , 1/16 W, 1% tol 0 , 1/10 W, 5% tol
NIC Components NIC Components
NRC04F64R9TRF NRC06Z0TRF
Rev. B | Page 49 of 52
AD9228
Item 35 Qty. 15 Reference Designator R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R431, R432, R433 R108, R110, R121, R122, R134, R136, R146, R147 R161, R162, R163, R164 R202, R203, R204 R222 R213 R229 R230, R319 Device Resistor Package 402 Value 1 k, 1/16 W, 1% tol Manufacturer NIC Components Manufacturer's Part Number NRC04F1001TRF
36
8
Resistor
402
33 , 1/16 W, 5% tol 499 , 1/16 W, 1% tol 100 k, 1/16 W, 1% tol 4.12 k, 1/16 W, 1% tol 49.9 , 1/16 W, 0.5% tol 4.99 k, 1/16 W, 5% tol 10 k, cermet trimmer potentiometer, 18-turn top adjust, 10%, 1/2 W 470 k, 1/16 W, 5% tol 39 k, 1/16 W, 5% tol 187 , 1/16 W, 1% tol 374 , 1/16 W, 1% tol 274 , 1/16 W, 1% tol 0 , 1/20 W, 5% tol
NIC Components NIC Components NIC Components NIC Components Susumu NIC Components BC Components
NRC04J330TRF
37 38 39 40 41 42
4 3 1 1 1 2
Resistor Resistor Resistor Resistor Resistor Potentiometer
402 402 402 402 402 3-lead
NRC04F4990TRF NRC04F1003TRF NRC04F4121TRF RR0510R-49R9-D NRC04F4991TRF CT94EW103
43 44 45
1 1 8
R228 R320 R307, R308, R309, R310, R407, R408, R409, R410 R305, R306, R405, R406 R316, R317, R415, R416 R245, R247, R249, R251, R253, R255, R257, R259, R261, R263, R265 R418 R419 R501 R240, R241 R242, R243 S401 T101, T102, T103, T104, T201 U501, U503
Resistor Resistor Resistor
402 402 402
NIC Components NIC Components NIC Components NIC Components NIC Components Panasonic
NRC04J474TRF NRC04J393TRF NRC04F1870TRF
46 47 48
4 4 11
Resistor Resistor Resistor
402 402 201
NRC04F3740TRF NRC04F2740TRF ERJ-1GE0R00C
49 50 51 52 53 54 55
1 1 1 2 2 1 5
Resistor Resistor Resistor Resistor Resistor Switch Transformer
402 402 603 402 402 SMD CD542
56
2
IC
SOT-223
4.75 k, 1/16 W, 1% tol 261 , 1/16 W, 1% tol 261 , 1/16 W, 1% tol 243 , 1/16 W, 1% tol 100 , 1/16 W, 1% tol Light touch, 100GE, 5 mm ADT1-1WT, 1:1 impedance ratio transformer ADP33339AKC-1.8, 1.5 A, 1.8 V LDO regulator
NIC Components NIC Components NIC Components NIC Components NIC Components Panasonic Mini-Circuits
NRC04J472TRF NRC04F2610TRF NRC06F2610TRF NRC04F2430TRF NRC04F1000TRF EVQ-PLDA15 ADT1-1WT+
Analog Devices
ADP33339AKCZ-1.8
Rev. B | Page 50 of 52
AD9228
Item 57 Qty. 2 Reference Designator U301, U401 Device IC Package LFCSP, CP-32 Value AD8332ACP, ultralow noise precision dual VGA ADP3339AKC-5 ADP3339AKC-3.3 AD9228BCPZ-65, quad, 12-bit, 65 MSPS serial LVDS 1.8 V ADC ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference AD9515BCPZ NC7WZ07 NC7WZ16 Flash prog mem 1k x 14, RAM size 64 x 8, 20 MHz speed, PIC12F controller series Manufacturer Analog Devices Manufacturer's Part Number AD8332ACPZ
58 59 60
1 1 1
U504 U502 U201
IC IC IC
SOT-223 SOT-223 LFCSP, CP-48-1
Analog Devices Analog Devices Analog Devices
ADP3339AKCZ-5 ADP3339AKCZ-3.3 AD9228BCPZ-65
61
1
U203
IC
SOT-23
Analog Devices
ADR510ARTZ
62 63 64 65
1 1 1 1
U202 U403 U404 U402
IC IC IC IC
LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC
Analog Devices Fairchild Fairchild Microchip
AD9515BCPZ NC7WZ07P6X_NL NC7WZ16P6X_NL PIC12F629-I/SN
1
This BOM is RoHS compliant.
Rev. B | Page 51 of 52
AD9228 OUTLINE DIMENSIONS
7.00 BSC SQ 0.60 MAX 0.60 MAX
37 36
0.30 0.23 0.18
48 1
PIN 1 INDICATOR
PIN 1 INDICATOR
TOP VIEW
6.75 BSC SQ
EXPOSED PAD
(BOTTOM VIEW)
5.25 5.10 SQ 4.95
0.50 0.40 0.30
25 24
12 13
0.25 MIN 5.50 REF
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
SEATING PLANE
0.20 REF
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 82. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm x 7 mm Body, Very Thin Quad (CP-48-1) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9228BCPZ-40 1 AD9228BCPZRL7-401 AD9228BCPZ-651 AD9228BCPZRL7-651 AD9228-65EB AD9228-65EBZ1
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel Evaluation Board Evaluation Board
Package Option CP-48-1 CP-48-1 CP-48-1 CP-48-1
Z = RoHS Compliant Part.
(c)2006-2007 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05727-0-7/07(B)
Rev. B | Page 52 of 52

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